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HIP4083
July 1996
80V, 300mA Three Phase High Side Driver
Description
The HIP4083 is a three phase high side N-channel MOSFET driver, specifically targeted for PWM motor control. Two HIP4083 may be used together for 3 phase full bridge applications (see application block diagram). Alternatively, the lower gates may be controlled directly from a buffered microprocessor output. Unlike other members of the HIP408x family, the HIP4083 has no built in turn-on delay. Each output (AHO, BHO, and CHO) will turn-on 65ns after its input is switched low. Likewise, each output will turn-off 60ns after its input is switched high. Very short and very long dead times are possible when two HIP4083 are used to drive a full bridge. This dead time is controlled by the input signal timing. The HIP4083 does not have a built in charge pump. Therefore, the bootstrap capacitors must be recharged on a periodic basis by initiating a short refresh pulse. In most bridge applications, this will happen automatically every time the lower FETs turn-on and the upper FETs turn-off. However, it is still possible to use the HIP4083 in applications that require the high side FETs to be on for extended periods of time. This can be easily accomplished by sending a short refresh pulse to the DIS pin. The HIP4083 has reduced drive current compared to the HIP4086 making it ideal for low to moderate power applications. The HIP4083 is optimized for applications where size and cost are important. For high power applications driving large power FETs, the HIP4086 is recommended.
Features
* Independently Drives Three High Side N-Channel MOSFETs in Three Phase Bridge Configuration * Bootstrap Supply Max Voltage to 95VDC * Bias Supply Operation from 7V to 15V * Drives 1000pF Load with Typical Rise Times of 35ns and Fall Times of 30ns * CMOS/TTL Compatible Inputs * Programmable Undervoltage Protection
Applications
* Brushless Motors * High Side Switches * AC Motor Drives * Switched Reluctance Motor Drives
Ordering Information
PART NUMBER HIP4083AB HIP4083AP TEMP. RANGE (oC) -40 to 105 -40 to 105 PACKAGE 16 Ld SOIC 16 Ld PDIP PKG. NO. M16.15 E16.3
Pinout
HIP4083 PDIP, SOIC TOP VIEW
Application Block Diagram
80V 12V AHI AHO BHO HIP4083 CHI CHO 16 CHB 15 CHO 14 CHS 13 UVLO 12 VDD 11 BHB 10 BHO 9 BHS MICROCONTROLLER (OPTIONAL) AHI BHI HIP4083 CHI CHO GND 12V AHO BHO GND BHI
AHI 1 BHI 2 CHI 3 DIS 4 VSS 5
AHB 6 AHO 7 AHS 8
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4223
12
HIP4083 Functional Block Diagram
6 DRIVER LEVEL SHIFTER AHI 1 UV 7 8 6 BHI 2 LOGIC CHI DIS 3 4 LEVEL SHIFTER UV EN DRIVER LEVEL SHIFTER UVLO 13 VDD 12 UNDERVOLTAGE DETECTOR UV UV 7 8 AHO AHS DRIVER 7 8 6 AHO AHS AHB AHO AHS AHB AHB
TRUTH TABLE INPUT AHI, BHI, CHI X X 1 0 UV 1 X 0 0 DIS X 1 0 0 OUTPUT AHO, BHO, CHO 0 0 0 1
NOTE: X signifies that input can be either a "1" or "0".
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HIP4083 Typical Application: Three Phase Bridge Driver with Programmable Dead Time
CHIP SUPPLY
CBYPASS 1 AHI OPTIONAL MICROPROCESSOR INPUTS 2 BHI 3 CHI 4 DIS 5 VSS 6 AHB 7 AHO CBS 8 AHS CHB 16 CHO 15 CHS 14 UVLO 13 VDD 12 BHB 11 BHO 10 BHS 9 OC SENSE RCURRENT
SENSE
POWER BUS CBS
CBS
1 AHI OPTIONAL MICROPROCESSOR INPUTS 2 BHI 3 CHI 4 DIS 5 VSS 6 AHB 7 AHO 8 AHS
CHB 16 CHO 15 CHS 14 UVLO 13 VDD 12 BHB 11 BHO 10 BHS 9 3-PHASE LOAD
Typical Application: High Side Switch
BOOT STRAP CAPACITOR 80V AND DIODE REQUIRED REFRESH 12V
DIS MICROPROCESSOR AHI BHI CHI GND HIP4083
AHO BHO CHO
LIGHT
14
HIP4083 Pin Descriptions
PIN NUMBER 6 11 16 SYMBOL AHB BHB CHB (xHB) DESCRIPTION Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full bridge applications. In this case, tie all three xHB pins to VDD and tie the xHS pins to the sources of the lower FETs. In full bridge applications, the lower FETs must be turned on first at start up to refresh the bootstrap capacitors. In high side switch applications, the load will keep xHS low and refresh should happen automatically at start up. Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When xHI is low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). If these pins are not driven, an internal 100A current source pulls them high. Chip ground. Undervoltage setting. A resistor can be connected between this pin and VSS to program the under voltage set point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this pin is tied to VDD, the undervoltage set point is typically 6.2V. Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100A pull-up holds DIS high when this pin is not driven. Gate connections. Connect to the gates of the power MOSFETs in each phase.
1 2 3
AHI BHI CHI (xHI) VSS UVLO
5 13
4
DIS
7 10 15
AHO BHO CHO (xHO) AHS BHS CHS (xHS)
8 9 14
MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap capacitors to these pins. In high side switch applications, 2mA of current will flow out of these pins into the load when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down to at least 7V below VDD. For example, when VDD = 12V, xHS must be pulled down to 5V. Therefore, the minimum load necessary for proper refresh is given by the following equation: RMIN = 5V/2mA = 2.5k. So in this case, if the load has an impedance less than 5k, refresh will happen automatically at start up. Positive supply rail. Bypass this pin to VSS with a capacitor >1F. In applications where the bus voltage and chip VDD are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly simplifies the filtering requirements.
12
VDD
15
HIP4083
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS. . . . . . . . . . -6V (Transient) to 85V (-40oC to 150oC) Voltage on xHB. . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V to +15V Voltage on xHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V Voltage on xHB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS +VDD Operating Ambient Temperature Range. . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS.
Electrical Specifications
VDD = VxHB = 12V, VSS = VxHS = 0V, Gate Capacitance (CGATE) = 1000pF, RUV = TJ = 25oC TJ = -40oC TO 150oC MAX MIN MAX UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current VDD Operating Current xHB On Quiescent Current xHB Off Quiescent Current xHB Operating Current VDD Rising Undervoltage Threshold VDD Falling Undervoltage Threshold Minimum Undervoltage Threshold INPUT PINS: AHI, BHI, CHI AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current VIN = 0V VIN = 5V 2.5 -145 -1 35 -100 1.0 -60 +1 2.7 -150 -10 0.8 -50 +10 V V mV A A xHI = 5V f = 20kHz, 50% Duty Cycle xHI = 0V xHI = 5V f = 20kHz, 50% Duty Cycle RUV OPEN RUV OPEN RUV = VDD 0.5 1.0 65 0.6 0.6 6.2 5.75 5.0 1.5 2.0 100 0.85 0.85 7.0 6.5 6.2 2.25 2.5 240 1.3 1.2 8.0 7.5 6.9 0.25 0.75 45 0.5 0.5 6.1 5.25 4.5 2.3 3.0 250 1.4 1.3 8.1 7.6 7.0 mA mA A mA mA V V V
GATE DRIVER OUTPUT PINS: AHO, BHO, AND CHO Average Turn-On Current Average Turn-Off Current VOUT 0V to 5V VOUT VDD to 4V 100 150 240 300 400 450 50 100 500 550 mA mA
16
HIP4083
Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF
TJ = 25oC PARAMETER Turn-Off Propagation Delay (xHI - xHO) Turn-On Propagation Delay (xHI - xHO) Rise Time (10 - 90%) Fall Time (90 - 10%) Disable Turn-Off Propagation Delay Disable to Output Enable (DIS - xHO) TEST CONDITIONS No Load No Load CGATE = 1000pF CGATE = 1000pF No Load No Load MIN TYP 60 65 35 30 65 70 MAX 80 90 60 50 TJS = -40oC TO 150oC MIN MAX 90 100 65 55 100 100 UNITS ns ns ns ns ns ns
Typical Performance Curves
2.0 VDD = 16V VDD = 12V 1.6 VDD = 10V 1.4 VDD = 8V VDD = 7V VDD = 15V 4.5 200kHz VDD SUPPLY CURRENT (mA) 100kHz 4.0 50kHz
VDD SUPPLY CURRENT (mA)
1.8
10kHz 3.5 20kHz
1.2
1.0 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140 160
3.0 -60 -40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140
160
FIGURE 1. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE
FIGURE 2. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY
950 xHB SUPPLY OFF CURRENT (A) 900 850 (VXHB - VXHS) = 10V 800 750
xHB ON SUPPLY CURRENT (A)
(VXHB - VXHS) = 15V (VXHB - VXHS) = 14V (VXHB - VXHS) = 13V (VXHB - VXHS) = 12V
120 110 100
(VXHB - VXHS) = 12V (VXHB - VXHS) = 10V (VXHB - VXHS) = 8V
(VXHB - VXHS) = 15V
(VXHB - VXHS) = 8V
90 80
(VXHB - VXHS) = 7V 700 650 -60
(VXHB - VXHS) = 7V 70 60 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120 140 160
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140 160
FIGURE 3. FLOATING SUPPLY OFF BIAS CURRENT
FIGURE 4. FLOATING SUPPLY ON BIAS CURRENT
17
HIP4083 Typical Performance Curves
4 CGATE = 1000pF xHB SUPPLY CURRENT (mA) xHB SUPPLY CURRENT (mA) 200kHz 3 200kHz 2.0
(Continued)
2.5 NO LOAD
100kHz 2 50kHz 1 20kHz 10kHz 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 120 140 160
1.5 100kHz 1.0 50kHz 20kHz 0.5 10kHz
0 -60 -40
-20
20 40 60 80 100 0 JUNCTION TEMPERATURE (oC)
120
140 160
FIGURE 5. FLOATING SUPPLY SWITCHING BIAS CURRENT
FIGURE 6. FLOATING SUPPLY SWITCHING BIAS CURRENT
10 UNDERVOLTAGE SHUTDOWN/ENABLE VOLTAGE (V) ENABLE (50K, UVLO TO GND) 9 TRIP (50K, UVLO TO GND) 8 ENABLE (UVLO OPEN) 7 TRIP (UVLO OPEN) 6 TRIP/ENABLE (OK, UVLO TO VDD) 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 PROPAGATION DELAY (ns)
100
DISABLE TURN-OFF 80 ENABLE TURN-ON TURN-OFF 60 TURN-ON
JUNCTION TEMPERATURE (oC)
40 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140 160
FIGURE 7. UNDERVOLTAGE THRESHOLD
FIGURE 8. PROPAGATION DELAY
50 AVERAGE TURN-ON CURRENT (A) CGATE = 1000pF RISE AND FALL TIME (ns)
0.35 15V 0.3 12V 0.25 10V 0.2 8V 0.15 7V 0.1 -60 0V TO 5V
40 TURN-ON TURN-OFF 30
20 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140 160
-40
-20
0
20
40
60
80
100
120 140 160
JUNCTION TEMPERATURE (oC)
FIGURE 9. RISE AND FALL TIME (10-90%)
FIGURE 10. GATE DRIVER AVERAGE TURN-ON CURRENT
18
HIP4083 Typical Performance Curves
0.5 AVERAGE TURN-OFF CURRENT (A) 15V 0.4 12V 10V 8V 0.2 7V 0.1 VDD TO 4V xHS LEAKAGE CURRENT (A) 40
(Continued)
50
0.3
30
20
10
0 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140 160
0 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)
120
140
160
FIGURE 11. GATE DRIVER AVERAGE TURN-OFF CURRENT
FIGURE 12. HIGH VOLTAGE LEAKAGE CURRENT
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HIP4083 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 16
2.93
20
HIP4083 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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